Data processing system

ABSTRACT

This case describes a find-first-one (FFO) instruction which is used to scan a table of 16-bit words which are successively addressed and loaded in an accumulator, the address being obtained by indexing the address of the first word with the contents of an index register which are successively increased by 1. Each time a word has been stored in the accumulator a find first one instruction FFO is executed. This instruction finds the leftmost 1-bit in this word, resets this bit in this word, and shifts the contents of the index register by four positions to the left. In this way the contents of the index register directly indicate the position of the leftmost 1-bit in the table.

United States Patent [1 1 Kobus et al.

[ DATA PROCESSING SYSTEM [75] Inventors: Stanislas Kobus, Palaiseau, France;

Juliaan Leo Gerard Janssens, Olmen; Willy Charles Jacques Zoile, St. Niklaas, both of Belgium [73] Assignees International Standard Electric Corporation, New York, N.Y.

[22] Filed: Nov. 29, 1972 [21] Appl. No.: 310,509

[30] Foreign Application Priority Data Dec. 10, 1971 Belgium 776495 [52] US. Cl. 340/1725 [51] Int. Cl. G06f 13/08; G06f 7/38 [58] Field of Search 340/1725 [56] References Cited UNITED STATES PATENTS 3,394,350 7/1968 Packard 340/1725 Dec. 30, 1975 3,504,349 Wallis 340/l72.5

57 ABSTRACT This case describes a find-first-one (FFO) instruction which is used to scan a table of 16-bit words which are successively addressed and loaded in an accumulator, the address being obtained by indexing the address of the first word with the contents of an index register which are successively increased by 1. Each time a word has been stored in the accumulator a find first one instruction FFO is executed. This instruction finds the leftmost l-bit in this word, resets this bit in this word, and shifts the contents of the index register by four positions to the left. In this way the contents of the index register directly indicate the position of the leftmost l-bit in the table.

1 Claim, 3 Drawing Figures v v v A P SIS DATA PROC ESSING SYSTEM The present invention relates to a data processing system with a processor and a memory storing a plurality of data words constituted by bits, said processor including an index register to store the relative address of a data word in a table of said memory, means to access this word from said table by using said relative address, and means to determine the position of the first bit of said word having a predetermined one of two conditions, all said bits of said word being ordered in a predetermined way.

Such a data processing system is already known from the Bell System Technical Journal, September l964, No 5, Part l,pages 1869-1870 and 1937. In this known system the bit position in the table thus determined is used to access a word from a second table. Since the number of bit positions in a word of the first table is relatively small only a like small number of words in the second table can be accessed.

An object of the present invention is therefore to provide a data processing system of the above type which permits to access a number of words from the second table which is a multiple of the number of bit positions in a word of the first table.

The present data processing system is particularly characterized in that said processor further includes means to combine said relative address and said position of said first bit in said word to obtain the position of said first bit in said memory table.

Another disadvantage of the above mentioned known data processing system is that, to access a word from the second table by using the bit position determined, an additional index register is required.

Another object of the present invention is therefore to provide a data processing system of the above type wherein no additional index register is required to access a word from the second table.

The present data processing system is also characterized in that said means to combine said relative address and said bit position in said word include means to juxtapose in said index register said bit position in said word and said relative address to obtain said bit position in said memory table.

The present invention also relates to a data processing system including a plurality of information storage devices, common communication means, gating means between said storage devices and said common communication means, control means to control said gating means in order to enable the transfer of information between said storage devices via said common communication means, and an adder circuit with which said storage devices are coupled, said adder circuit having an augend input, an addend input and a summing output.

Such a data processing system is well known in the computer art and it is a further object of the present invention to provide a data processing system wherein an optimum use is made of the adder circuit.

According to the present invention this object is attained due to the fact that said common communication means are constituted by said adder circuit, the one and the other storage devices of each pair of storage devices between which information must be transferred being coupled to at least one of said adder circuit inputs and to said adder circuit output via said gating means respectively.

In accordance with a preferred embodiment of the invention the present data processing system includes a memory and a processor with an index register, an accumulator register, an adder circuit having 16 augend inputs, l6 addend inputs and i6 summing outputs, and a find-first-one circuit the 16 inputs of which are coupled to the l6 outputs of the accumulator register and the four outputs of which are coupled to the last four augend inputs, whilst the 12 remaining augend inputs are coupled to the last 12 outputs of the index register. The 16 summing outputs of the adder circuit are coupled to the 16 inputs of the index register. After a word of a first table has been accessed by using a relative address (of this word in this table) stored in the index register and after this word has been stored in the accumulator register, the system is able to execute a find-first-one instruction on this word. This instruction consists in operating the find-first-one circuit to find the leftmost l-bit in the word stored in the accumulator register, to apply the bit position then appearing at the outputs of this circuit and a portion of the contents of the index register to the above mentioned augend inputs and to insert the result appearing at the above summing outputs in the index register. This index register thus indicates the position in the table of the leftmost bit found, this position constituting the relative address of a word of a second table.

The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein:

FIG. 1 represents a data processing system according to the present invention;

FIG. 2 shows the register A of FIG. 1 in more detail;

FIG. 3 shows part of the circuit ADGC of FIG. 1 and other circuitry in more detail.

Principally referring to FIG. 1 the data processing system shown therein is constituted by a memory MEM and by a processor constituted by an arithmetic unit AU and a control unit CU.

The memory MEM is adapted to store a plurality of 16-bit instruction words such as LDA, LDX, STA, STX, FFO and JDX and a plurality of 16-bit data words such as S1 and S2. The memory further includes the tables of data words UT and IJSBT.

The arithmetic unit AU includes a 16-bit buffer register M, a 16-bit memory location register Y, a 16-bit index register X, a 16-bit accumulator register A, a 16-bit programme counter P to store the address of an instruction being or to be executed and a well known adder unit ADU constituted by an adder gating circuit ADGC and an adder circuit ADC proper.

The control unit CU includes a control device CD to control the various operations of the system by gene rating gating signals gs -gs at the appropriate times and a 7-bit register F to store the operation code of an instruction. The register F is connected to the control device CD. It should be noted that the gating signals gs to gs are in fact each constituted by 15 signals g n(x00) g 0o(is) to Shalom-8 151151- 35 will become Clear later.

The inputs of the cells to of the memory register M are coupled to the outputs of the corresponding output cells to 5 of the memory MEM is schematically indicated by the arrow interconnecting MEM and M and pointing to M. The inputs of the seven cells no to 06 of the register F are connected to the outputs of the connected to the inputs of the output cells on to 15 of 5 memory MEM via gating means GMM -GMM, controlled by the gating signals gs generated by the control device CD. The outputs VO -YO of the cells on to of the register Y are connected to the addressing input of the memory MEM as schematically indicated by the arrow interconnecting Y and MEM and point to MEM. This connection includes the AND-gates GY to GY which are controlled by the gating signals gs provided by the control device CD.

The outputs MO -M0 XO XO AO rAO and (O -YO of the cells to of the memory register M, of the index register X, of the accumulator A and of the register Y are connected to the augend inputs AG to AG of the adder circuit ADC via the individual AND-gates COM -GUM GGX GGX GGA GGA and GGY GGY, respectively and via the common OR-gates MAG MAG, These four groups of AND-gates are controlled by the gating signals ,gs to gs, generated by the control device CD respectively. The outputs MO -M0 XO XO AO AO PO PO of the cells to of the memory register M, of the index register X, of the accumulator A and of the programme counter P are connected to the addend inputs AD to AD of the adder circuit ADC via the individual AND-gates GAM GAM GAX -GAX GAA GAA GAP -GAP respectively and via the common OR-gates MAD MAD These four groups of AND gates are controlled by the gating signals gs and gs generated by the control device CD. The 16 sum outputs SM SM, of the adder circuit ADC are connected to the inputs Yl YI Xl -XI Al -Al and Pl -Pl of the cells on to 15 of the registers Y, X, A and of the counter P via the AND-gates GSY -GSY GSX -GSX, GSA -GSA and GSP -GSP which are controlled by the gating signals gs to gs respectively. The above mentioned AND- and OR-gates connected to the adder circuit ADC form the adder gating circuit ADGC.

It should be noted that the register A has further outputs AF to AF which are connected to third inputs of the AND-gates GAA to 0AA via the AND-gates GAA to GAA' which are controlled by the gating signals gs and the inverters I' to I' respectively. The register A also has outputs F0 to F0 which are connected to the adder circuit ADC, as will be explained later.

Principally referring to FIG. 2 the register A shown therein includes the register AR proper with the above mentioned cells on to having the outputs A0 to A0 These outputs are connected to a find-first-one circuit FFOC including 15 AND-gates GA to GA the one inputs of which are connected to the outputs A0 to A0 of the register AR respectively. The other inputs of each of these AND-gates GA to GA are each connected via an inverter to all those of the outputs A0 to A0,, which precede the gate in the row shown e.g. the single other input of the AND-gate GA is connected to the output of the single preceding output A0 via the inverter l the 14 other inputs of the AND-gate GA are connected to the outputs of the 14 preceding outputs A0 to A0 via the inverters I to l respectively. The outputs AF to AF, of the AND- gates GA to GA and the output AF which is di- 4 rectly connected to the output A0 of the cell of the register AR are connected to the coder circuit CC which is adapted to code the 16-bit code applied to its input in a 4-bit code which then appears at its outputs F0 to PO Principally referring to FIG. 3 the latter shows in more detail the connections, already shown in FIG. 1, between the outputs A0 to A0 of the register A and the addend inputs AD to AD of the adder circuit ADC and between the summing outputs SM to SM of this adder circuit ADC, on the one hand, and the inputs Al to A] of the register A and Xl to XI of the index register X, on the other hand. Hereby the gates GAA -GAA GSA GSA and GSX GSX are controlled by the gating signals gs gs t2(00) g 12(15) and g moor'g uusi respectively- FIG. 3 also shows connections, not represented in FIG. 1, between the index register outputs XO XO and the coder circuit outputs FO -F0 on the one hand, and the augend inputs AG AG,, and A6,. AG of the adder circuit ADC, on the other hand. These connections are realized via the AND-gates (1X to GX and GF to CF respectively, these groups of gates being controlled by the gating signals mom-g uun and g mlzig ims) respectively, Provided by the control device CD.

With regard to the flow charts given at the end of the description the following should be noted with respect to the instructions which will be used in the description of the operation of the data processing system.

Each of the classical instructions LDA, LDX, STA, STX is constituted by a 7-bit function code, including the addressing mode, and a 9-bit address part:

the LDA(LDX) instructions are adapted to control the replacement of the contents of the register A(X) by those of the memory location found at the effective address, i.e., at the address calculated by means of the address part of the instruction and taking the addressing mode thereof into account. If to find the effective address use is made of the contents of the index register X these instructions are indicated by LDA' (LDX');

- the STA (STX) instructions are adapted to control the replacement of the contents of the memory location found at the effective address by those of the register A(X).

The classical instruction JDX is constituted by a function code and an address part and is adapted to control the following operations:

decrement the contents of the index register X by one;

if the result is not zero jump to the instruction having the address stored in the JDX instruction;

if the result is zero execute the immediately following instruction.

The instruction FFO is constituted by a function code and is adapted to control the execution of the following operations:

check the contents of the register A;

- if zero skip one instruction; if not zero execute the following steps in sequence.

store the contents of the cells M to of the register X in the cells 00 to thereof;

- store the conditions of the outputs F0 to F0 of the coder circuit CC of the register A in the cells 2 to of the register X;

- reset to zero the first l-bit found in the register A.

Reference being made to the drawings and to the flow charts the operation of the present data processing system is described in detail hereinafter. Hereby it is assumed that this system controls a classical toll telephone switching network (not shown), the data processed being for instance:

information about the open and closed conditions of the loops formed between calling distant exchanges and incoming junctors of this switching network. These loop conditions are indicated by a 1-bit (closed) or a -bit (open) and are stored in the [6-bit words of an incomingjunctor table UT in the memory MEM, one bit being provided per incoming unctor;

-- information about the calls being processed and involving the above mentioned incoming junctors, such information being for instance the identity of the register connected to an incomingjunctor, the identity of an outgoing junctor connected to an incomingjunctor, etc. These status information are stored in the 16-bit words of an incoming junctor status buffer table USBT. one such word being for instance provided per incoming junctor.

As will appear from the description the present data processing system is particularly useful to scan only those words of the IJSBT which correspond to incoming junctors to which a closed loop has been established, i.e., for which a 1-bit is registered in the UT.

First of all it should be noted that at the end of the execution of an instruction the following instruction is already read in the memory MEM and that the instruction read-out is only available after a certain time interval.

It is now supposed that during the execution of an instruction the reading of an LDX instruction in the memory MEM has been started by means of the address of this LDX instruction, this address being stored at that moment in the register Y and in the programme counter P.

A time interval later the addressed 16-bit LDX instruction is received in the register M and the 7-bit function or operation code of this instruction stored in the bits 0 to 6 thereof is transferred into the register F of the control unit CU. This code is decoded in the control device CD which subsequently generates gating signals to control the execution of the various operations indicated by the LDX instruction. Under the control of these gating signals the address part of the LDX instruction stored in the cells 1 to of the memory register M is transferred to the corresponding cells 1 to of the register Y by making use of the adder unit ADU. By using either the augend or the addend inputs of this adder unit ADU the latter functions indeed as a communication bus since the information applied to these augend or addend inputs appears unmodified at the summing outputs of the adder circuit ADC.

The control device CD of the control unit CU activates the control inputs of the gates GGM to GGM, by means of the gating signals gs to gs and of the gates GGSY to GSY by means of the gating signals gs to gs due to which the address part of the LDX instruction is transferred to the cells to of the register Y. It is supposed that this address part is the complete or partial address of the memory location wherein the relative address of the last word of the table HT is stored, this relative address being the address with respect to that of the table, i.e., with respect to the first word of this table.

With the address part stored in the register Y, possibly combined with another address, the memory MEM is then addressed as a result of which the relative address of the last word of the IJT is received in the memory register M. Under control of the control device CD this address is then transferred to the index register X by again making use of the adder unit ADU and more particularly by activating the control inputs of the gates GGM to GGM, and GSX to GSX by means of the g g g 8 03 (00) to 8 03 um and 8 11 mm to 8 11 (15) respectively.

Previously the programme counter P has been incremented by I so that the address of the following instruction to be executed then appears in this counter. Now this address is stored in the register Y and used to address the memory MEM. This instruction is supposed to be an STX instruction. The control device CD also controls the clearing of the M and F registers.

it should be noted that the above described LDX instruction is classical in the computer art and has also been described in relative detail to make clear the use of the adder unit ADU as a communication bus. The LDA, STA, STX and .IDX instructions which are also well known per se in the computer art will therefore only be very briefly described hereinafter.

When the STX instruction has been received in the memory register M and its function code has been stored in the register F the control device CD controls the storage of the contents of the X register in the word S1 of the memory MEM without however modifying the contents of this X register. This operation is necessary since the contents of the X register will be moditied and since at a certain moment its original contents must be available, as will become clear later. During the execution of this STX instruction the programme counter P is incremented by 1 so that the address of the next instruction which is an LDA instruction appears therein. This address is also stored in the Y register and used to address the memory MEM. it is supposed that the address stored in the LDA' instruction is the effective address of the first word of the UT.

After the LDA' instruction has been received in the memory register M and its function code has been stored in the register F the control device CD controls the transfer of the address part of this LDA' instruction from the M register to the Y register. It also controls the storage of the contents of the X register in the Y register and the combination of the effective address of the first word of the UT and the relative address of the last word of this table to obtain the effective address of this last word. By means of this effective address the memory MEM is addressed so that some time afterwards the last word of the LIT is received in the memory register M from which it is transferred to the register A by making use of the adder unit ADU. Under control of the control device CD the programme counter P is incremented by l so that the address of the next instruction which is an FFO instruction appears therein. This address is also stored in the Y register and used to address the memory MEM. Also the M and F registers are cleared.

After the FFO instruction has been received in the memory register M and its function code has been stored in the register F the control device CD controls the various operations indicated by the FFO.

First it is checked whether the contents of the A register are zero or not. This is done by checking the output of an OR-gate (not shown) the inputs of which are connected to the outputs A to AO of this A register.

1f the contents of the A register are zero the contents of the programme counter P are incremented by 2 and the address of the JDX instruction which then appears therein is stored in the Y register and used to address the memory MEM. The registers M and F are cleared. After the JDX instruction has been received in the memory register M and its function code has been stored in the register F the control device CD controls the operations indicated by the JDX instruction. More particularly under its control the contents of the X register are decremented by 1 after which it is checked if these contents are different from zero or not by checking the output of an OR-gate (not shown) the inputs of which are connected to the outputs X0 to X0 of the X register. If the contents of the X register are zero the programme counter P is incremented by 1 and the address of the following instruction which then appears therein is stored in the Y register and used to address the memory MEM. The registers M and F are cleared. If the contents of the X register however are not zero the contents of the programme counter P are decremented so that the address of the above STX instruction again appears therein. Consequently the above described operations are then repeated.

1f the contents of the A register are different from zero the contents of the programme counter P are incremented by 1 so that the address of the STA in struction appears therein. This address is also stored in the Y register and used to address the memory MEM. The control device CD also controls the execution of the operations indicated by the FFO instruction. Before describing these operations it should be noted that when the word stored in the A register and more partic ularly in the register AR (FIG. 2) is only the input AF of the coder circuit CC is activated. Indeed:

the input AF is not activated since the output A0 is not activated;

- the outputs AF (not shown) to AF, of the gates GA (not shown) to (3A are not activated since in the FFOC one of the control inputs of each of these gates is connected to the activated output A (not shown) via an inverter l (not shown).

The one-out-of-l6 code 010 0 0 0 00 00 00 0 00 0 thus applied to the coder circuit CC by the FFOC is coded therein in a 4-bit binary code 0001 which appears at the outputs F0 to F0 This code indicates that the first l-bit found is the second bit of the word.

The operations of the PFC instruction controlled by the control device CD are the following, it being supposed that the contents of the X register are This address indicates word 14 of the UT, i.e., the fifteenth word of this table.

First the conditions 0 0 0 0 0 0 0 0 l l l 0 of the outputs XO to XO of the cells 04 to 15 of the X register and the conditions 0 0 0 l of the outputs FO to FO of the coder circuit CC of the A register are stored in the cells 00 to of the X register via the gates GX to GX GF to GF and GSX to GSX,,, of the adder gating circuit ADGC of the adder unit ADU, these gates being controlled by the gating signals gs -gs and gs -gs generated by the control device 8 CD. In this way the word finally stored in the X register is 00O00000l1l0000l This word indicates the position in the table UT of the above first bit found. Indeed, it indicates the position 225 in this table and this is correct since the l-bit found is the second bit of the fifteenth word of this table.

From the above it follows that the position of the first l-bit in a word of the table UT has been combined with the position of this word in the table UT to obtain the position of this first l-bit in the table IJT.

Afterwards the first l-bit found in the A register is reset to 0. This is done by storing the contents of all the cells of the A register again in these cells, except for the cell in which the above first l-bit was found to a 0 being registered in the latter cell. This operation is performed again by using the adder unit ADU and by applying enabling Signals 8 1s (om-8 1s (I5) 8 05 (om-8 0a [15) and 8 12 -gs to the control inputs of the gates GAA' to GAA', GAA to GAA and GSA to GSA respectively. Since the outputs of the inverters I' to l' form the code word lOllllllllllllll,

the gates GAA and GAA to GAA are enabled, whereas gate GAA (not shown) is inhibited. Consequently the conditions of the outputs A0. and A0 to A0 are stored in the cells and 02 to of the A register, whereas a 0 is registered in cell The following word is hence finally registered in the A register When a FFO instruction is executed on this word another first l-bit will be found.

When the following instruction which is an STA instruction is read from the memory MEM, it is received in the memory register M and the function code of this instruction is stored in the F register. The control device CD then controls the execution of the various operations indicated by this STA instruction. More particularly the contents of the A register are stored in the word S2 of the memory MEM so that it remains available for later use. The address of this word is stored in the address part of the STA instruction. The control device CD also controls the incrementing by 1 of the programme counter P which then indicates the address of an LDA' instruction to be executed. This address is also stored in the Y register and used to address the memory MEM. Further, the control device CD also clears the registers M and F.

After the above LDA' instruction has been received in the memory register M and the function code of this instruction is stored in the F register the control device CD controls the execution of the various operations indicated by this LDA' instruction the address part of which is that of the first word of the table lJSBT. Under the control of this control device CD the latter address is then combined with the address stored in the X register and constituted by the position of a 1-bit in the table 1.1T to obtain the address of a word in the table lJSBT. By means of the latter address of table [1881" is then addressed and the information then received in the memory register M is further processed in a way which will not be described here since it is without importance. for the present invention.

10 be accessed so that the higher the number of bits in the table UT the higher the number of words in the table USBT may be.

While the principles of the invention have been de scribed above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

What is claimed is:

l. A data processing system with a processor and a memory (MEM) for storing a plurality of n-bit data words, comprising:

an index register (X) having n stages for storing in the n m last stages a relative address of a data word in a table of said memory; an accumulator (A) having an accumulator register (AR) for storing therein said data word;

coder means (FFOC, CC) for determining the m-bit position of the first bit of said data word having a predetermined one of two conditions, all said bits of said word being ordered in a predetermined way, said accumulator coupled to said coder means and said m-bit position being provided at the m-bit output (PO -F of said accumulator (A);

JDX

first means for coupling said memory (MEM) and said accumulator register (AR);

means for accessing a data word from said memory table by using said relative address and for storing said word in said accumulator register (AR) via said first coupling means; and

second means for coupling said It m last stages of 

1. A data processing system with a processor and a memory (MEM) for storing a plurality of n-bit data words, comprising: an index register (X) having n stages for storing in the n - m last stages a relative address of a data word in a table of said memory; an accumulator (A) having an accumulator register (AR) for storing therein said data word; coder means (FFOC, CC) for determining the m-bit position of the first bit of said data word having a predetermined one of two conditions, all said bits of said word being ordered in a predetermined way, said accumulator coupled to said coder means and said m-bit position being provided at the m-bit output (FO00-FO03) of said accumulator (A); first means for coupling said memory (MEM) and said accumulator register (AR); means for accessing a data word from said memory table by using said relative address and for storing said word in said accumulator register (AR) via said first coupling means; and second means for coupling said n - m last stages of said index register (X) and the m-bit output (FO00-FO03) of said accumulator (A) with the n - m first stages and the m last stages of said index register respectively, whereby said n - m bit relative address of said word and said m-bit position of said bit in said word are combined to obtain in said index register (X) the position of said bit in said memory table. 